In a memory system for a computer or for other electronic devices, one or more memory devices are typically coupled to a memory controller via a shared bus. Memory devices may include volatile memory devices such as random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), and/or non-volatile memory devices such as NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), such as spin torque transfer random access memory (STT RAM).
A memory system can include a number of discrete memory devices. Each memory device is typically provided as an integrated semiconductor circuit or “package,” where each package includes one or more targets. A target is a unit of memory that is enabled by a particular chip enable signal. Each target in a package may include one or more logical units of memory. A logical unit refers to a unit of memory storage that can independently execute commands and/or report status. Each logical unit may include an array of memory formed on a single semiconductor die, for example.
A package including a single target with a single logical unit is typically referred to as a single-die package (SDP). A package including multiple logical units formed on multiple semiconductor dice is typically referred to as a multi-chip package (MCP). An MCP can include a number of memory dice (also referred to as “chips”), where each die has one or more logical units associated therewith. For example, a dual die package (DDP) may include two logical units on two dice arranged as part of a single target (i.e., both logical units are referenced by a single chip enable signal) or arranged as two separate targets (i.e., each logical unit is referenced by a separate chip enable signal). Similarly, a quadruple die package (QDP) may include four logical units arranged as two separate targets (i.e., two logical units are referenced by a single chip enable signal) or arranged as four separate targets (i.e., each logical unit is referenced by a separate chip enable signal). Similar arrangements for packages including eight or more dice are also known in the art.
FIG. 1 shows a conventional memory device 100 including four logical units 110-113 formed on four separate dice. Logical units 110-113 each include at least one array of memory cells, such as NAND memory cells, or other types of memory that are known in the art. During an initialization process of memory device 100, each of logical units 110-113 is assigned a separate logical unit address, in order to enable the writing and retrieving of information stored on each logical unit 110-113. Typically, the address of each logical unit within device 100 includes a three-bit binary address, in order to accommodate up to eight logical units to be addressed separately in each package. In memory device 100, each logical unit 110-113 is assigned an address using three separate address input contacts mds<0>, mds<1>, and mds<2>. Address input contacts mds<0>, mds<1>, mds<2> are typically bond pads that are capable of being electrically connected to a device voltage pad 105 (e.g., Vcc) to establish the three bit address.
An address input contact electrically connected to device voltage 105 indicates a first logic signal (e.g., a logic high signal), while an address input contact that is not electrically connected to device voltage 105 indicates a second logic signal (e.g., a logic low signal). Accordingly, each logical unit 110-113 receives a unique three-bit logical address which may be hardwired during packaging of memory device 100. Alternatively, one of address input contacts mds<0>, mds<1>, mds<2> may be designated for receiving a signal that indicates whether the respective logical unit 110-113 is part of a memory device 100 having a QDP arrangement, commonly referred to as a “QDP enable” signal. In such an arrangement, the QDP enable address input contact is activated in each of logical units 110-113 (i.e., mds<1>), with the other address input contacts (i.e., mds<0> and mds<2>) being used to assign a respective two bit address for each of logical units 110-113.
FIG. 2 shows a functional block diagram for control circuitry 210 that may be found in each conventional logical unit (e.g., logical units 110-113) of memory device 100 (FIG. 1). Control circuitry 210 includes an input/output control circuit 220 for controlling the transfer of data, command, and address signals to and from the logical unit and control logic 221 for controlling internal operations of the logical unit. Control circuitry 210 is operably coupled to a memory section 226 of the logical unit for storing data. The memory section 226 may include an array 228 of memory cells, which may be NAND flash or other types of memory cells. Programming and readout of memory section 226 is controlled by row decoder 231 and column decoder 227. Memory section 226 also includes a data register 229 and cache register 230, as discussed further below.
Data, command, and address signals received by control circuitry 210 are multiplexed onto a single set of pins DQ[7:0] that is received by the input/output control circuit 220. Input/output control circuit 220 also receives a data strobe signal DQS that provides a synchronous reference for data input and output operations.
Input/output control 220 is coupled to an address register 222, a status register 223, and a command register 224. Address information received by input/output control circuit 220 is latched into address register 222. The latched address information is sent by address register 222 to a row decoder 231 and/or a column decoder 227 in memory section 226. Commands received by input/output control circuit 220 are latched by command register 224, and the latched commands are transferred from command register 224 to control logic 221 for generating internal signals to control internal operations of the logical unit. Data received by input/output control circuit 220 is transferred to cache register 230 and data register 229 for storage in array 228. Status register 223 is controlled by control logic 221 to report the status of the logical unit to the input/output control circuit 220.
In addition to receiving address control signals 225 from address input contacts mds<0>, mds<1>, mds<2> (FIG. 1), control logic 221 receives several external control signals. For example, control logic 221 typically receives a chip enable signal CE# for enabling or disabling the logical unit, a command latch enable signal CLE for loading a command from input/output control 220 into command register 224, an address latch enable signal ALE for loading an address from input/output control circuit 220 into address register 222, a clock signal CLK for controlling internal operations of the logical unit, a write/read enable signal W/R# for controlling whether input/output control circuit 220 is transmitting or receiving data, and a write protect signal WP# that enables or disables programming and/or erasing of data stored in memory section 226. Control logic 221 may also include an open-drain active low output 232 that outputs a ready/busy signal R/B# indicating target array activity.
Logical units 110-113 (FIG. 1) require a separate external contact for each separate control signal that control logic 221 is configured to receive, including for each of address control signals 225 (i.e., mds<0>, mds<1>, mds<2>). Each of these external contacts increases the required surface area at a perimeter of the logical unit, preventing further reduction in the size of each logical unit 110-113 (FIG. 1), and thus of the overall package 100. In addition, the number of logical units that can be packaged within a memory device is limited by the number of unique logical unit addresses that can be assigned to the logical units, and thus by the number of address control signals that the logical unit is capable of receiving. A reduction in the number of external pins would save die space and simplify memory device package processing.